The present invention relates to improved arrangements for a ferroelectric memory.
Various ferroelectric materials are known, such as Phase III potassium nitrate, bismuth titanate and the PZT family of lead zirconate and titanate compounds, for example. One characteristic of such materials is a hysteresis curve or loop of the sort illustrated in FIG. 1 wherein the abscissa represents the field voltage applied to the material and the ordinate represents the polarization of the material. That is, because of the hysteresis curve, if a capacitor is formed using a ferroelectric material between its plates, the flow of current through the capacitor will depend on the prior history of the voltages applied to the device. Briefly, if a ferroelectric capacitor is in an initial state wherein zero volts is applied, it may have a polarization indicated at point A in FIG. 1, illustratively. A physical characteristic of the device will be its so called "coercive voltage" represented by a broken line B. If a positive voltage greater than the coercive voltage B is applied across the capacitor, then the capacitor will conduct current and move to a new polarization represented by point C. When the voltage is brought to zero, rather than returning to the polarization represented at A, the ferroelectric capacitor instead will maintain essentially the same polarization, as indicated at point D. A further positive voltage will cause relatively little change in the polarization, moving it toward or beyond point C. However, a substantial enough negative voltage will cause the polarization to vary as represented by point E. Thereafter, when such negative voltage is removed from the capacitor, the polarization of the device remains essentially the same and moves to point A. Thus, points A and D represent two states occurring at zero volts applied across the capacitor but depending on the history of voltage applied to the device.
Consequently, a ferroelectric capacitor is usable as part of a memory cell. Point A can represent a logic "zero," and point D can represent a logic "one." Typically, a ferroelectric capacitor has metallic or conductive plates typically 500 angstroms to 100 micrometers apart with a ferroelectric material such as potassium nitrate as the dielectric between the plates. See, for example, Rohrer U.S. Pat. Nos. 3,728,694 ("Thin Film Ferroelectric Device") issued Apr. 17, 1973; 4,195,355 ("Process For Manufacturing A Ferroelectric Device And Devices Manufactured Thereby") issued Mar. 25, 1980; and 3,939,292 ("Process For Stable Phase III Potassium Nitrate And Articles Prepared Therefrom") issued Feb. 17, 1976, all of whose disclosures are hereby incorporated herein.
To determine the state of a ferroelectric capacitor, one can apply a voltage pulse, observe the current which flows and thereby determine the state. To write into a ferroelectric capacitor cell, one applies a positive or negative voltage to the plates of the capacitor, causing the ferroelectric material therewithin to move along its hysteresis curve as shown in FIG. 1, forcing it into a stable state corresponding to the data, a binary one or a binary zero. To read, if a positive pulse is applied and there is relatively little current drawn or charge moved by the capacitor, then this would indicate that the capacitor was in state D. If substantial charge moved, this would indicate that the capacitor was in state A.
It will be appreciated that if a read operation occurs and a significant amount of charge moves to cause the capacitor to move from one stable state to the other along the hysteresis curve, then the data within the cell will be flipped, as the cell will have moved to the opposite stable state which represents the opposite binary digit. Consequently, restoration is usually needed when reading a memory cell using a ferroelectric capacitor as the memory element.
The prior art has used ferroelectric capacitors as memory cells, and it has been the standard practice to provide an orthogonal arrangement of rows and columns with a memory cell coupling each row to each column at the plural intersections. FIG. 2 represents such a prior art arrangement with nine memory cells arranged in three columns C0, C1 and C2 intersecting three rows R0, R1 and R2. Each intersection has a corresponding ferroelectric capacitor representing a memory cell, and it is noted that each row conductor is connected directly to one of the capacitor plates while each column conductor is connected directly to the other capacitor plates. It will be assumed that the coercive voltage of the ferroelectric capacitors is between three and four volts. To select a memory cell 10, a positive voltage (illustratively 5 volts) is applied to row R0 and thus to the top capacitor plates of capacitors 10, 12 and 14. Zero volts is applied to the other rows R1 and R2. Also, zero volts is applied to the column C0 (and hence the bottom plate of capacitor 10), so that the voltage across capacitor 10 is five volts. The amount of current which flows indicates the data stored in capacitor 10. To prevent reading the other cells of the array, the voltage across capacitor 16 is controlled to be zero volts, which is less than the coercive voltage. Hence, capacitor 16 does not change state. However, if zero volts is applied to column C1 or C2, then the voltage across capacitors 12 and 14 in row R0 will be five volts, which exceeds the coercive voltage. Thus, all cells 10, 12, and 14 in row R0 would be accessed. To prevent this, columns C1 and C2 are controlled to have one-half of the full read voltage applied to them. Thus, 2.5 volts is applied to columns C1 and C2, so that the total voltage across capacitors 12 and 14 each is only 2.5 volts. Because 2.5 volts is less than the coercive voltage, those cells ought to remain in the stable state in which they started. Thus, only cell 10 at the intersection of row R0 and column C0 can be accessed for reading in this manner.
Having read memory cell 10, one ordinarily must restore it back to its original stable state. To do this, five volts is placed on column C0 and zero volts on row R0. Each of rows R1 and R2 are brought to 2.5 volts, and columns C1 and C2 are brought to zero volts.
Circuitry able to accommodate these sequences of voltage combinations is complex, impedes the objective of achieving high speed in the memory, and takes space. One object of the present invention therefore is to provide a simpler design or arrangement for ferroelectric capacitor memory cells which will overcome this need for elaborate circuitry for switching rows and columns among various voltage combinations in order to read and restore the memory cells.
Another problem associated with prior art ferroelectric memories is a "disturb signal." Most, if not all, ferroelectrics have a coercive voltage, i.e., a small voltage applied to the capacitor for a long enough time can cause the capacitor to change state. For example, if a ferroelectric capacitor in state A (FIG. 1) has a voltage of 2.5 volts applied across it for a long enough time, then even though the coercive voltage may be between three and four volts, the capacitor may move to state D. A further object of the present invention is to reduce these "disturb voltage" or "disturb signal" effects.
A third problem addressed by the present invention is that it has traditionally been thought that if a ferroelectric material has no clear coercive voltage, then it is not usable in a memory. This problem also is overcome by the present invention.